SPEC CPU(R)2017 Floating Point Speed Result Cisco Systems Cisco UCS C220 M6 (Intel Xeon Gold 5318S, 2.10GHz) CPU2017 License: 9019 Test date: Aug-2021 Test sponsor: Cisco Systems Hardware availability: Apr-2021 Tested by: Cisco Systems Software availability: Dec-2020 Base Base Base Peak Peak Peak Benchmarks Threads Run Time Ratio Threads Run Time Ratio --------------- ------- --------- --------- ------- --------- --------- 603.bwaves_s 48 94.3 625 S 48 94.0 628 * 603.bwaves_s 48 94.5 624 * 48 93.8 629 S 603.bwaves_s 48 95.6 617 S 48 95.1 620 S 607.cactuBSSN_s 48 77.6 215 * 48 77.6 215 * 607.cactuBSSN_s 48 77.5 215 S 48 77.5 215 S 607.cactuBSSN_s 48 78.3 213 S 48 78.3 213 S 619.lbm_s 48 43.5 120 * 48 43.5 120 * 619.lbm_s 48 42.0 125 S 48 42.0 125 S 619.lbm_s 48 44.1 119 S 48 44.1 119 S 621.wrf_s 48 95.7 138 S 48 90.8 146 * 621.wrf_s 48 96.9 136 S 48 90.3 146 S 621.wrf_s 48 96.0 138 * 48 91.1 145 S 627.cam4_s 48 74.5 119 S 48 74.5 119 S 627.cam4_s 48 73.4 121 S 48 73.4 121 S 627.cam4_s 48 73.6 120 * 48 73.6 120 * 628.pop2_s 48 164 72.3 * 48 164 72.3 * 628.pop2_s 48 163 72.9 S 48 163 72.9 S 628.pop2_s 48 165 72.0 S 48 165 72.0 S 638.imagick_s 48 79.6 181 * 48 79.6 181 * 638.imagick_s 48 79.7 181 S 48 79.7 181 S 638.imagick_s 48 79.4 182 S 48 79.4 182 S 644.nab_s 48 60.6 288 * 48 61.2 285 S 644.nab_s 48 60.6 288 S 48 61.2 286 * 644.nab_s 48 60.6 288 S 48 61.1 286 S 649.fotonik3d_s 48 90.1 101 S 48 88.3 103 * 649.fotonik3d_s 48 89.1 102 * 48 88.5 103 S 649.fotonik3d_s 48 88.1 104 S 48 87.8 104 S 654.roms_s 48 73.6 214 S 48 73.6 214 S 654.roms_s 48 73.9 213 S 48 73.9 213 S 654.roms_s 48 73.8 213 * 48 73.8 213 * ================================================================================= 603.bwaves_s 48 94.5 624 * 48 94.0 628 * 607.cactuBSSN_s 48 77.6 215 * 48 77.6 215 * 619.lbm_s 48 43.5 120 * 48 43.5 120 * 621.wrf_s 48 96.0 138 * 48 90.8 146 * 627.cam4_s 48 73.6 120 * 48 73.6 120 * 628.pop2_s 48 164 72.3 * 48 164 72.3 * 638.imagick_s 48 79.6 181 * 48 79.6 181 * 644.nab_s 48 60.6 288 * 48 61.2 286 * 649.fotonik3d_s 48 89.1 102 * 48 88.3 103 * 654.roms_s 48 73.8 213 * 48 73.8 213 * SPECspeed(R)2017_fp_base 172 SPECspeed(R)2017_fp_peak 173 HARDWARE -------- CPU Name: Intel Xeon Gold 5318S Max MHz: 3400 Nominal: 2100 Enabled: 48 cores, 2 chips Orderable: 1,2 Chips Cache L1: 32 KB I + 48 KB D on chip per core L2: 1.25 MB I+D on chip per core L3: 36 MB I+D on chip per chip Other: None Memory: 1 TB (32 x 32 GB 2Rx4 PC4-3200V-R, running at 2933) Storage: 1 x 300 GB 15K SAS HDD Other: None SOFTWARE -------- OS: SUSE Linux Enterprise Server 15 SP2 5.3.18-22-default Compiler: C/C++: Version 2021.1 of Intel oneAPI DPC++/C++ Compiler Build 20201113 for Linux; Fortran: Version 2021.1 of Intel Fortran Compiler Classic Build 20201112 for Linux; C/C++: Version 2021.1 of Intel C/C++ Compiler Classic Build 20201112 for Linux Parallel: Yes Firmware: Version 4.2.1c released Jul-2021 File System: btrfs System State: Run level 3 (multi-user) Base Pointers: 64-bit Peak Pointers: 64-bit Other: jemalloc memory allocator V5.0.1 Power Management: BIOS and OS set to prefer performance at the cost of additional power usage Operating System Notes ---------------------- Stack size set to unlimited using "ulimit -s unlimited" Environment Variables Notes --------------------------- Environment variables set by runcpu before the start of the run: KMP_AFFINITY = "granularity=fine,compact" LD_LIBRARY_PATH = "/home/cpu2017/lib/intel64:/home/cpu2017/je5.0.1-64" MALLOC_CONF = "retain:true" OMP_STACKSIZE = "192M" General Notes ------------- Binaries compiled on a system with 1x Intel Core i9-7980XE CPU + 64GB RAM memory using Redhat Enterprise Linux 8.0 Transparent Huge Pages enabled by default Prior to runcpu invocation Filesystem page cache synced and cleared with: sync; echo 3> /proc/sys/vm/drop_caches NA: The test sponsor attests, as of date of publication, that CVE-2017-5754 (Meltdown) is mitigated in the system as tested and documented. Yes: The test sponsor attests, as of date of publication, that CVE-2017-5753 (Spectre variant 1) is mitigated in the system as tested and documented. Yes: The test sponsor attests, as of date of publication, that CVE-2017-5715 (Spectre variant 2) is mitigated in the system as tested and documented. jemalloc, a general purpose malloc implementation built with the RedHat Enterprise 7.5, and the system compiler gcc 4.8.5 sources available from jemalloc.net or https://github.com/jemalloc/jemalloc/releases Platform Notes -------------- BIOS Settings: Adjacent Cache Line Prefetcher set to Disabled DCU Streamer Prefetch set to Disabled UPI Link Enablement set to 1 UPI Power Management set to Enabled Sub NUMA Clustering set to Disabled LLC Dead Line set to Disabled Memory Refresh Rate set to 1x Refresh ADDDC Sparing set to Disabled Patrol Scrub set to Disabled Enhanced CPU performance set to Auto Energy Efficient Turbo set to Enabled Processor C6 Report set to Enabled Processor C1E set to Enabled Intel HyperThreading Technology set to Disabled Sysinfo program /home/cpu2017/bin/sysinfo Rev: r6622 of 2021-04-07 982a61ec0915b55891ef0e16acafc64d running on localhost Sat Aug 14 03:30:47 2021 SUT (System Under Test) info as seen by some common utilities. For more information on this section, see https://www.spec.org/cpu2017/Docs/config.html#sysinfo From /proc/cpuinfo model name : Intel(R) Xeon(R) Gold 5318S CPU @ 2.10GHz 2 "physical id"s (chips) 48 "processors" cores, siblings (Caution: counting these is hw and system dependent. The following excerpts from /proc/cpuinfo might not be reliable. Use with caution.) cpu cores : 24 siblings : 24 physical 0: cores 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 physical 1: cores 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 From lscpu from util-linux 2.33.1: Architecture: x86_64 CPU op-mode(s): 32-bit, 64-bit Byte Order: Little Endian Address sizes: 46 bits physical, 57 bits virtual CPU(s): 48 On-line CPU(s) list: 0-47 Thread(s) per core: 1 Core(s) per socket: 24 Socket(s): 2 NUMA node(s): 2 Vendor ID: GenuineIntel CPU family: 6 Model: 106 Model name: Intel(R) Xeon(R) Gold 5318S CPU @ 2.10GHz Stepping: 6 CPU MHz: 2402.794 CPU max MHz: 3400.0000 CPU min MHz: 800.0000 BogoMIPS: 4200.00 Virtualization: VT-x L1d cache: 48K L1i cache: 32K L2 cache: 1280K L3 cache: 36864K NUMA node0 CPU(s): 0-23 NUMA node1 CPU(s): 24-47 Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 invpcid_single ssbd mba ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 hle avx2 smep bmi2 erms invpcid rtm cqm rdt_a avx512f avx512dq rdseed adx smap avx512ifma clflushopt clwb intel_pt avx512cd sha_ni avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local wbnoinvd dtherm ida arat pln pts hwp hwp_act_window hwp_epp hwp_pkg_req avx512vbmi umip pku ospke avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg tme avx512_vpopcntdq la57 rdpid md_clear pconfig flush_l1d arch_capabilities /proc/cpuinfo cache data cache size : 36864 KB From numactl --hardware WARNING: a numactl 'node' might or might not correspond to a physical chip. available: 2 nodes (0-1) node 0 cpus: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 node 0 size: 515649 MB node 0 free: 508765 MB node 1 cpus: 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 node 1 size: 516086 MB node 1 free: 514109 MB node distances: node 0 1 0: 10 20 1: 20 10 From /proc/meminfo MemTotal: 1056498052 kB HugePages_Total: 0 Hugepagesize: 2048 kB /sys/devices/system/cpu/cpu*/cpufreq/scaling_governor has performance From /etc/*release* /etc/*version* os-release: NAME="SLES" VERSION="15-SP2" VERSION_ID="15.2" PRETTY_NAME="SUSE Linux Enterprise Server 15 SP2" ID="sles" ID_LIKE="suse" ANSI_COLOR="0;32" CPE_NAME="cpe:/o:suse:sles:15:sp2" uname -a: Linux localhost 5.3.18-22-default #1 SMP Wed Jun 3 12:16:43 UTC 2020 (720aeba) x86_64 x86_64 x86_64 GNU/Linux Kernel self-reported vulnerability status: CVE-2018-12207 (iTLB Multihit): Not affected CVE-2018-3620 (L1 Terminal Fault): Not affected Microarchitectural Data Sampling: Not affected CVE-2017-5754 (Meltdown): Not affected CVE-2018-3639 (Speculative Store Bypass): Mitigation: Speculative Store Bypass disabled via prctl and seccomp CVE-2017-5753 (Spectre variant 1): Mitigation: usercopy/swapgs barriers and __user pointer sanitization CVE-2017-5715 (Spectre variant 2): Mitigation: Enhanced IBRS, IBPB: conditional, RSB filling CVE-2020-0543 (Special Register Buffer Data Sampling): Not affected CVE-2019-11135 (TSX Asynchronous Abort): Not affected run-level 3 Aug 13 23:11 SPEC is set to: /home/cpu2017 Filesystem Type Size Used Avail Use% Mounted on /dev/sda2 btrfs 222G 37G 184G 17% /home From /sys/devices/virtual/dmi/id Vendor: Cisco Systems Inc Product: UCSC-C220-M6S Serial: WZP24430ADF Additional information from dmidecode 3.2 follows. WARNING: Use caution when you interpret this section. The 'dmidecode' program reads system data which is "intended to allow hardware to be accurately determined", but the intent may not be met, as there are frequent changes to hardware, firmware, and the "DMTF SMBIOS" standard. Memory: 32x 0xCE00 M393A4K40DB3-CWE 32 GB 2 rank 3200, configured at 2933 BIOS: BIOS Vendor: Cisco Systems, Inc. BIOS Version: C220M6.4.2.1c.1.0701210708 BIOS Date: 07/01/2021 BIOS Revision: 5.22 (End of data from sysinfo program) Compiler Version Notes ---------------------- ============================================================================== C | 619.lbm_s(base, peak) 638.imagick_s(base, peak) | 644.nab_s(base) ------------------------------------------------------------------------------ Intel(R) C Intel(R) 64 Compiler Classic for applications running on Intel(R) 64, Version 2021.1 Build 20201112_000000 Copyright (C) 1985-2020 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ ============================================================================== C | 644.nab_s(peak) ------------------------------------------------------------------------------ Intel(R) oneAPI DPC++/C++ Compiler for applications running on Intel(R) 64, Version 2021.1 Build 20201113 Copyright (C) 1985-2020 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ ============================================================================== C | 619.lbm_s(base, peak) 638.imagick_s(base, peak) | 644.nab_s(base) ------------------------------------------------------------------------------ Intel(R) C Intel(R) 64 Compiler Classic for applications running on Intel(R) 64, Version 2021.1 Build 20201112_000000 Copyright (C) 1985-2020 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ ============================================================================== C | 644.nab_s(peak) ------------------------------------------------------------------------------ Intel(R) oneAPI DPC++/C++ Compiler for applications running on Intel(R) 64, Version 2021.1 Build 20201113 Copyright (C) 1985-2020 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ ============================================================================== C++, C, Fortran | 607.cactuBSSN_s(base, peak) ------------------------------------------------------------------------------ Intel(R) C++ Intel(R) 64 Compiler Classic for applications running on Intel(R) 64, Version 2021.1 Build 20201112_000000 Copyright (C) 1985-2020 Intel Corporation. All rights reserved. Intel(R) C Intel(R) 64 Compiler Classic for applications running on Intel(R) 64, Version 2021.1 Build 20201112_000000 Copyright (C) 1985-2020 Intel Corporation. All rights reserved. Intel(R) Fortran Intel(R) 64 Compiler Classic for applications running on Intel(R) 64, Version 2021.1 Build 20201112_000000 Copyright (C) 1985-2020 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ ============================================================================== Fortran | 603.bwaves_s(base, peak) 649.fotonik3d_s(base, peak) | 654.roms_s(base, peak) ------------------------------------------------------------------------------ Intel(R) Fortran Intel(R) 64 Compiler Classic for applications running on Intel(R) 64, Version 2021.1 Build 20201112_000000 Copyright (C) 1985-2020 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ ============================================================================== Fortran, C | 621.wrf_s(base, peak) 627.cam4_s(base, peak) | 628.pop2_s(base, peak) ------------------------------------------------------------------------------ Intel(R) Fortran Intel(R) 64 Compiler Classic for applications running on Intel(R) 64, Version 2021.1 Build 20201112_000000 Copyright (C) 1985-2020 Intel Corporation. All rights reserved. Intel(R) C Intel(R) 64 Compiler Classic for applications running on Intel(R) 64, Version 2021.1 Build 20201112_000000 Copyright (C) 1985-2020 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ Base Compiler Invocation ------------------------ C benchmarks: icc Fortran benchmarks: ifort Benchmarks using both Fortran and C: ifort icc Benchmarks using Fortran, C, and C++: icpc icc ifort Base Portability Flags ---------------------- 603.bwaves_s: -DSPEC_LP64 607.cactuBSSN_s: -DSPEC_LP64 619.lbm_s: -DSPEC_LP64 621.wrf_s: -DSPEC_LP64 -DSPEC_CASE_FLAG -convert big_endian 627.cam4_s: -DSPEC_LP64 -DSPEC_CASE_FLAG 628.pop2_s: -DSPEC_LP64 -DSPEC_CASE_FLAG -convert big_endian -assume byterecl 638.imagick_s: -DSPEC_LP64 644.nab_s: -DSPEC_LP64 649.fotonik3d_s: -DSPEC_LP64 654.roms_s: -DSPEC_LP64 Base Optimization Flags ----------------------- C benchmarks: -m64 -std=c11 -xCORE-AVX2 -ipo -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=4 -qopenmp -DSPEC_OPENMP -mbranches-within-32B-boundaries Fortran benchmarks: -m64 -Wl,-z,muldefs -DSPEC_OPENMP -xCORE-AVX2 -ipo -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=4 -qopenmp -nostandard-realloc-lhs -mbranches-within-32B-boundaries -L/usr/local/jemalloc64-5.0.1/lib -ljemalloc Benchmarks using both Fortran and C: -m64 -std=c11 -Wl,-z,muldefs -xCORE-AVX2 -ipo -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=4 -qopenmp -DSPEC_OPENMP -mbranches-within-32B-boundaries -nostandard-realloc-lhs -L/usr/local/jemalloc64-5.0.1/lib -ljemalloc Benchmarks using Fortran, C, and C++: -m64 -std=c11 -Wl,-z,muldefs -xCORE-AVX2 -ipo -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=4 -qopenmp -DSPEC_OPENMP -mbranches-within-32B-boundaries -nostandard-realloc-lhs -L/usr/local/jemalloc64-5.0.1/lib -ljemalloc Peak Compiler Invocation ------------------------ C benchmarks (except as noted below): icc 644.nab_s: icx Fortran benchmarks: ifort Benchmarks using both Fortran and C: ifort icc Benchmarks using Fortran, C, and C++: icpc icc ifort Peak Portability Flags ---------------------- Same as Base Portability Flags Peak Optimization Flags ----------------------- C benchmarks: 619.lbm_s: basepeak = yes 638.imagick_s: basepeak = yes 644.nab_s: -m64 -Wl,-z,muldefs -xCORE-AVX2 -Ofast -ffast-math -flto -mfpmath=sse -funroll-loops -fiopenmp -DSPEC_OPENMP -qopt-mem-layout-trans=4 -fimf-accuracy-bits=14:sqrt -mbranches-within-32B-boundaries -L/usr/local/jemalloc64-5.0.1/lib -ljemalloc Fortran benchmarks: 603.bwaves_s: -m64 -Wl,-z,muldefs -prof-gen(pass 1) -prof-use(pass 2) -DSPEC_SUPPRESS_OPENMP -DSPEC_OPENMP -ipo -xCORE-AVX2 -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=4 -qopenmp -nostandard-realloc-lhs -mbranches-within-32B-boundaries -L/usr/local/jemalloc64-5.0.1/lib -ljemalloc 649.fotonik3d_s: Same as 603.bwaves_s 654.roms_s: basepeak = yes Benchmarks using both Fortran and C: 621.wrf_s: -m64 -std=c11 -Wl,-z,muldefs -prof-gen(pass 1) -prof-use(pass 2) -ipo -xCORE-AVX2 -O3 -no-prec-div -qopt-prefetch -ffinite-math-only -qopt-mem-layout-trans=4 -DSPEC_SUPPRESS_OPENMP -qopenmp -DSPEC_OPENMP -mbranches-within-32B-boundaries -nostandard-realloc-lhs -L/usr/local/jemalloc64-5.0.1/lib -ljemalloc 627.cam4_s: basepeak = yes 628.pop2_s: basepeak = yes Benchmarks using Fortran, C, and C++: 607.cactuBSSN_s: basepeak = yes The flags files that were used to format this result can be browsed at http://www.spec.org/cpu2017/flags/Intel-ic2021-official-linux64_revA.html http://www.spec.org/cpu2017/flags/Cisco-Platform-Settings-V1.0-ICX-revG.html You can also download the XML flags sources by saving the following links: http://www.spec.org/cpu2017/flags/Intel-ic2021-official-linux64_revA.xml http://www.spec.org/cpu2017/flags/Cisco-Platform-Settings-V1.0-ICX-revG.xml SPEC CPU and SPECspeed are registered trademarks of the Standard Performance Evaluation Corporation. All other brand and product names appearing in this result are trademarks or registered trademarks of their respective holders. ---------------------------------------------------------------------------------------------------------------------------------- For questions about this result, please contact the tester. For other inquiries, please contact info@spec.org. Copyright 2017-2021 Standard Performance Evaluation Corporation Tested with SPEC CPU(R)2017 v1.1.8 on 2021-08-14 03:30:47-0400. Report generated on 2021-09-01 14:25:47 by CPU2017 text formatter v6255. Originally published on 2021-08-31.