SPEC CPU®2017 Integer Rate Result

Copyright 2017-2020 Standard Performance Evaluation Corporation

Hewlett Packard Enterprise (Test Sponsor: HPE)

Synergy 480 Gen10
(2.90 GHz, Intel Xeon Gold 6226R)

SPECrate®2017_int_base = 21300

SPECrate®2017_int_peak = Not Run

CPU2017 License: 3 Test Date: Jun-2020
Test Sponsor: HPE Hardware Availability: Nov-2019
Tested by: HPE Software Availability: Sep-2019

Benchmark result graphs are available in the PDF report.

Hardware
CPU Name: Intel Xeon Gold 6226R
  Max MHz: 3900
  Nominal: 2900
Enabled: 32 cores, 2 chips, 2 threads/core
Orderable: 1, 2 chip(s)
Cache L1: 32 KB I + 32 KB D on chip per core
  L2: 1 MB I+D on chip per core
  L3: 22 MB I+D on chip per chip
  Other: None
Memory: 384 GB (24 x 16 GB 2Rx8 PC4-2933Y-R)
Storage: 1 x 400 GB SAS SSD, RAID 0
Other: None
Software
OS: SUSE Linux Enterprise Server 15 SP1 (x86_64)
Kernel 4.12.14-195-default
Compiler: C/C++: Version 19.0.5.281 of Intel C/C++
Compiler Build 20190815 for Linux;
Fortran: Version 19.0.5.281 of Intel Fortran
Compiler Build 20190815 for Linux;
Parallel: No
Firmware: HPE BIOS Version I42 (11/13/2019) released Nov-2019
File System: btrfs
System State: Run level 3 (multi-user)
Base Pointers: 64-bit
Peak Pointers: Not Applicable
Other: None
Power Management: BIOS set to prefer performance at the cost of additional power usage

Results Table

Benchmark Base Peak
Copies Seconds Ratio Seconds Ratio Seconds Ratio Copies Seconds Ratio Seconds Ratio Seconds Ratio
SPECrate®2017_int_base 21300
SPECrate®2017_int_peak Not Run
Results appear in the order in which they were run. Bold underlined text indicates a median measurement.
500.perlbench_r 64 663 154 664 153 662 154
502.gcc_r 64 530 171 531 171 527 172
505.mcf_r 64 395 262 394 262 393 263
520.omnetpp_r 64 581 145 582 144 583 144
523.xalancbmk_r 64 261 259 259 261 260 260
525.x264_r 64 250 448 250 448 250 449
531.deepsjeng_r 64 403 182 403 182 403 182
541.leela_r 64 622 170 636 167 636 167
548.exchange2_r 64 408 411 407 412 406 413
557.xz_r 64 522 133 523 132 522 132

Compiler Notes

The build date 20190815 in sw_compiler is correct for the IC compiler.
The build_date in Compiler Version Notes is incorrect.

Submit Notes

 The numactl mechanism was used to bind copies to processors. The config file option 'submit'
 was used to generate numactl commands to bind each copy to a specific processor.
 For details, please see the config file.

Operating System Notes

 Stack size set to unlimited using "ulimit -s unlimited"
 Transparent Huge Pages enabled by default
 Prior to runcpu invocation
 Filesystem page cache synced and cleared with:
 sync; echo 3 >       /proc/sys/vm/drop_caches

Environment Variables Notes

Environment variables set by runcpu before the start of the run:
LD_LIBRARY_PATH =
     "/home/cpu2017/lib/intel64:/home/cpu2017/lib/ia32:/home/cpu2017/je5.0.1-
     32"
MALLOC_CONF = "retain:true"

General Notes

 Binaries compiled on a system with 2x Intel(R) Xeon(R) Gold 6258R CPU  + 384GB RAM
 memory using SUSE Linux Enterprise Server 15 SP1 (x86_64)
NA: The test sponsor attests, as of date of publication, that CVE-2017-5754 (Meltdown)
is mitigated in the system as tested and documented.
Yes: The test sponsor attests, as of date of publication, that CVE-2017-5753 (Spectre variant 1)
is mitigated in the system as tested and documented.
Yes: The test sponsor attests, as of date of publication, that CVE-2017-5715 (Spectre variant 2)
is mitigated in the system as tested and documented.

Platform Notes

 BIOS Configuration:
  Thermal Configuration set to Maximum Cooling
  Memory Patrol Scrubbing set to Disabled
  LLC Prefetch set to Enabled
  LLC Dead Line Allocation set to Disabled
  Enhanced Processor Performance set to Enabled
  Workload Profile set to General Throughput Compute
  Workload Profile set to Custom
   Energy/Performance Bias set to Balanced Performance

 Sysinfo program /home/cpu2017/bin/sysinfo
 Rev: r6365 of 2019-08-21 295195f888a3d7edb1e6e46a485a0011
 running on sy480-sys2 Wed Jun  3 19:29:54 2020

 SUT (System Under Test) info as seen by some common utilities.
 For more information on this section, see
    https://www.spec.org/cpu2017/Docs/config.html#sysinfo

 From /proc/cpuinfo
    model name : Intel(R) Xeon(R) Gold 6226R CPU @ 2.90GHz
       2  "physical id"s (chips)
       64 "processors"
    cores, siblings (Caution: counting these is hw and system dependent. The following
    excerpts from /proc/cpuinfo might not be reliable.  Use with caution.)
       cpu cores : 16
       siblings  : 32
       physical 0: cores 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
       physical 1: cores 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

 From lscpu:
      Architecture:        x86_64
      CPU op-mode(s):      32-bit, 64-bit
      Byte Order:          Little Endian
      Address sizes:       46 bits physical, 48 bits virtual
      CPU(s):              64
      On-line CPU(s) list: 0-63
      Thread(s) per core:  2
      Core(s) per socket:  16
      Socket(s):           2
      NUMA node(s):        4
      Vendor ID:           GenuineIntel
      CPU family:          6
      Model:               85
      Model name:          Intel(R) Xeon(R) Gold 6226R CPU @ 2.90GHz
      Stepping:            7
      CPU MHz:             2900.000
      BogoMIPS:            5800.00
      Virtualization:      VT-x
      L1d cache:           32K
      L1i cache:           32K
      L2 cache:            1024K
      L3 cache:            22528K
      NUMA node0 CPU(s):   0-7,32-39
      NUMA node1 CPU(s):   8-15,40-47
      NUMA node2 CPU(s):   16-23,48-55
      NUMA node3 CPU(s):   24-31,56-63
      Flags:               fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov
      pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp
      lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid
      aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16
      xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave
      avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cdp_l3
      invpcid_single intel_ppin ssbd mba ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi
      flexpriority ept vpid fsgsbase tsc_adjust bmi1 hle avx2 smep bmi2 erms invpcid rtm
      cqm mpx rdt_a avx512f avx512dq rdseed adx smap clflushopt clwb intel_pt avx512cd
      avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total
      cqm_mbm_local dtherm ida arat pln pts pku ospke avx512_vnni md_clear flush_l1d
      arch_capabilities

 /proc/cpuinfo cache data
    cache size : 22528 KB

 From numactl --hardware  WARNING: a numactl 'node' might or might not correspond to a
 physical chip.
   available: 4 nodes (0-3)
   node 0 cpus: 0 1 2 3 4 5 6 7 32 33 34 35 36 37 38 39
   node 0 size: 96287 MB
   node 0 free: 95932 MB
   node 1 cpus: 8 9 10 11 12 13 14 15 40 41 42 43 44 45 46 47
   node 1 size: 96735 MB
   node 1 free: 96538 MB
   node 2 cpus: 16 17 18 19 20 21 22 23 48 49 50 51 52 53 54 55
   node 2 size: 96764 MB
   node 2 free: 96580 MB
   node 3 cpus: 24 25 26 27 28 29 30 31 56 57 58 59 60 61 62 63
   node 3 size: 96566 MB
   node 3 free: 96312 MB
   node distances:
   node   0   1   2   3
     0:  10  21  31  31
     1:  21  10  31  31
     2:  31  31  10  21
     3:  31  31  21  10

 From /proc/meminfo
    MemTotal:       395627408 kB
    HugePages_Total:       0
    Hugepagesize:       2048 kB

 From /etc/*release* /etc/*version*
    os-release:
       NAME="SLES"
       VERSION="15-SP1"
       VERSION_ID="15.1"
       PRETTY_NAME="SUSE Linux Enterprise Server 15 SP1"
       ID="sles"
       ID_LIKE="suse"
       ANSI_COLOR="0;32"
       CPE_NAME="cpe:/o:suse:sles:15:sp1"

 uname -a:
    Linux sy480-sys2 4.12.14-195-default #1 SMP Tue May 7 10:55:11 UTC 2019 (8fba516)
    x86_64 x86_64 x86_64 GNU/Linux

 Kernel self-reported vulnerability status:

 CVE-2018-3620 (L1 Terminal Fault):        Not affected
 Microarchitectural Data Sampling:         Not affected
 CVE-2017-5754 (Meltdown):                 Not affected
 CVE-2018-3639 (Speculative Store Bypass): Mitigation: Speculative Store Bypass disabled
                                           via prctl and seccomp
 CVE-2017-5753 (Spectre variant 1):        Mitigation: __user pointer sanitization
 CVE-2017-5715 (Spectre variant 2):        Mitigation: Enhanced IBRS, IBPB: conditional,
                                           RSB filling

 run-level 3 Jun 3 19:25

 SPEC is set to: /home/cpu2017
    Filesystem     Type   Size  Used Avail Use% Mounted on
    /dev/sda2      btrfs  371G  207G  163G  57% /home

 From /sys/devices/virtual/dmi/id
     BIOS:    HPE I42 11/13/2019
     Vendor:  HPE
     Product: Synergy 480 Gen10
     Product Family: Synergy
     Serial:  MXQ72204FC

 Additional information from dmidecode follows.  WARNING: Use caution when you interpret
 this section. The 'dmidecode' program reads system data which is "intended to allow
 hardware to be accurately determined", but the intent may not be met, as there are
 frequent changes to hardware, firmware, and the "DMTF SMBIOS" standard.
   Memory:
     24x UNKNOWN NOT AVAILABLE 16 GB 2 rank 2933

 (End of data from sysinfo program)

Compiler Version Notes

==============================================================================
C       | 500.perlbench_r(base) 502.gcc_r(base) 505.mcf_r(base)
        | 525.x264_r(base) 557.xz_r(base)
------------------------------------------------------------------------------
Intel(R) C Compiler for applications running on Intel(R) 64, Version 19.0.5
  NextGen Technology Build 20190729
Copyright (C) 1985-2019 Intel Corporation. All rights reserved.
------------------------------------------------------------------------------

==============================================================================
C++     | 520.omnetpp_r(base) 523.xalancbmk_r(base) 531.deepsjeng_r(base)
        | 541.leela_r(base)
------------------------------------------------------------------------------
Intel(R) C++ Compiler for applications running on Intel(R) 64, Version 19.0.5
  NextGen Technology Build 20190729
Copyright (C) 1985-2019 Intel Corporation. All rights reserved.
------------------------------------------------------------------------------

==============================================================================
Fortran | 548.exchange2_r(base)
------------------------------------------------------------------------------
Intel(R) Fortran Intel(R) 64 Compiler for applications running on Intel(R)
  64, Version 19.0.5.281 Build 20190815
Copyright (C) 1985-2019 Intel Corporation.  All rights reserved.
------------------------------------------------------------------------------

Base Compiler Invocation

C benchmarks:

 icc 

C++ benchmarks:

 icpc 

Fortran benchmarks:

 ifort 

Base Portability Flags

500.perlbench_r:  -DSPEC_LP64   -DSPEC_LINUX_X64 
502.gcc_r:  -DSPEC_LP64 
505.mcf_r:  -DSPEC_LP64 
520.omnetpp_r:  -DSPEC_LP64 
523.xalancbmk_r:  -DSPEC_LP64   -DSPEC_LINUX 
525.x264_r:  -DSPEC_LP64 
531.deepsjeng_r:  -DSPEC_LP64 
541.leela_r:  -DSPEC_LP64 
548.exchange2_r:  -DSPEC_LP64 
557.xz_r:  -DSPEC_LP64 

Base Optimization Flags

C benchmarks:

 -m64   -std=c11   -Wl,-z,muldefs   -xCORE-AVX512   -Ofast   -flto   -mfpmath=sse   -funroll-loops   -qnextgen   -fuse-ld=ld   -qopt-mem-layout-trans=4   -L/opt/intel/compilers_and_libraries_2019.5.281/linux/compiler/lib/intel64_lin   -lqkmalloc 

C++ benchmarks:

 -m64   -Wl,-z,muldefs   -xCORE-AVX512   -Ofast   -flto   -mfpmath=sse   -funroll-loops   -qnextgen   -fuse-ld=ld   -qopt-mem-layout-trans=4   -L/opt/intel/compilers_and_libraries_2019.5.281/linux/compiler/lib/intel64_lin   -lqkmalloc 

Fortran benchmarks:

 -m64   -Wl,-z,muldefs   -xCORE-AVX512   -O3   -ipo   -no-prec-div   -qopt-mem-layout-trans=4   -nostandard-realloc-lhs   -L/opt/intel/compilers_and_libraries_2019.5.281/linux/compiler/lib/intel64_lin   -lqkmalloc 

The flags files that were used to format this result can be browsed at
http://www.spec.org/cpu2017/flags/HPE-Platform-Flags-Intel-V1.2-CLX-revB.html,
http://www.spec.org/cpu2017/flags/Intel-ic19.0u5-official-linux64_revD.2020-06-23.html.

You can also download the XML flags sources by saving the following links:
http://www.spec.org/cpu2017/flags/HPE-Platform-Flags-Intel-V1.2-CLX-revB.xml,
http://www.spec.org/cpu2017/flags/Intel-ic19.0u5-official-linux64_revD.2020-06-23.xml.