SPEC(R) CINT2006 Summary Hewlett Packard Enterprise ProLiant DL560 Gen10 (3.60 GHz, Intel Xeon Gold 5122) Test Sponsor: HPE Mon Nov 20 11:28:47 2017 CPU2006 License: 3 Test date: Nov-2017 Test sponsor: HPE Hardware availability: Oct-2017 Tested by: HPE Software availability: Sep-2017 Base Base Base Peak Peak Peak Benchmarks Copies Run Time Rate Copies Run Time Rate -------------- ------ --------- --------- ------ --------- --------- 400.perlbench 32 404 774 * 400.perlbench 32 405 773 S 400.perlbench 32 403 776 S 401.bzip2 32 599 516 S 401.bzip2 32 601 514 S 401.bzip2 32 600 514 * 403.gcc 32 317 812 S 403.gcc 32 314 821 S 403.gcc 32 315 817 * 429.mcf 32 183 1590 S 429.mcf 32 183 1600 * 429.mcf 32 183 1600 S 445.gobmk 32 506 664 S 445.gobmk 32 506 663 * 445.gobmk 32 506 663 S 456.hmmer 32 184 1620 S 456.hmmer 32 185 1620 * 456.hmmer 32 186 1600 S 458.sjeng 32 551 703 * 458.sjeng 32 551 703 S 458.sjeng 32 550 703 S 462.libquantum 32 31.0 21400 S 462.libquantum 32 31.0 21400 * 462.libquantum 32 30.7 21600 S 464.h264ref 32 603 1180 S 464.h264ref 32 600 1180 S 464.h264ref 32 600 1180 * 471.omnetpp 32 373 536 S 471.omnetpp 32 373 536 * 471.omnetpp 32 373 537 S 473.astar 32 349 644 S 473.astar 32 351 641 * 473.astar 32 352 639 S 483.xalancbmk 32 148 1490 S 483.xalancbmk 32 149 1480 * 483.xalancbmk 32 150 1470 S ============================================================================== 400.perlbench 32 404 774 * 401.bzip2 32 600 514 * 403.gcc 32 315 817 * 429.mcf 32 183 1600 * 445.gobmk 32 506 663 * 456.hmmer 32 185 1620 * 458.sjeng 32 551 703 * 462.libquantum 32 31.0 21400 * 464.h264ref 32 600 1180 * 471.omnetpp 32 373 536 * 473.astar 32 351 641 * 483.xalancbmk 32 149 1480 * SPECint(R)_rate_base2006 1140 SPECint_rate2006 Not Run HARDWARE -------- CPU Name: Intel Xeon Gold 5122 CPU Characteristics: Intel Turbo Boost Technology up to 3.70 GHz CPU MHz: 3600 FPU: Integrated CPU(s) enabled: 16 cores, 4 chips, 4 cores/chip, 2 threads/core CPU(s) orderable: 1, 2, 4 chip(s) Primary Cache: 32 KB I + 32 KB D on chip per core Secondary Cache: 1 MB I+D on chip per core L3 Cache: 16.5 MB I+D on chip per chip Other Cache: None Memory: 384 GB (48 x 8 GB 2Rx8 PC4-2666V-R) Disk Subsystem: 1 x 960 GB SATA SSD, RAID 0 Other Hardware: None SOFTWARE -------- Operating System: SUSE Linux Enterprise Server 12 (x86_64) SP2 Kernel 4.4.21-68-default Compiler: C/C++: Version 18.0.0.128 of Intel C/C++ Compiler for Linux Auto Parallel: No File System: xfs System State: Run level 3 (multi-user) Base Pointers: 32-bit Peak Pointers: Not Applicable Other Software: Microquill SmartHeap V10.2 Submit Notes ------------ The numactl mechanism was used to bind copies to processors. The config file option 'submit' was used to generate numactl commands to bind each copy to a specific processor. For details, please see the config file. Operating System Notes ---------------------- Stack size set to unlimited using "ulimit -s unlimited" Transparent Huge Pages enabled by default Filesystem page cache cleared with: shell invocation of 'sync; echo 3 > /proc/sys/vm/drop_caches' prior to run runspec command invoked through numactl i.e.: numactl --interleave=all runspec irqbalance disabled with "service irqbalance stop" tuned profile set wtih "tuned-adm profile throughput-performance" VM Dirty ratio was set to 40 using "echo 40 > /proc/sys/vm/dirty_ratio" Numa balancing was disabled using "echo 0 > /proc/sys/kernel/numa_balancing" Platform Notes -------------- BIOS Configuration: Thermal Configuration set to Maximum Cooling LLC Prefetch set to Enabled LLC Dead Line Allocation set to Disabled Memory Patrol Scrubbing set to Disabled Workload Profile set to General Throughput Compute Minimum Processor Idle Power Core C-State set to C1E Sysinfo program /home/cpu2006/config/sysinfo.rev6993 Revision 6993 of 2015-11-06 (b5e8d4b4eb51ed28d7f98696cbe290c1) running on linux-mcua Mon Nov 20 11:28:49 2017 This section contains SUT (System Under Test) info as seen by some common utilities. To remove or add to this section, see: http://www.spec.org/cpu2006/Docs/config.html#sysinfo From /proc/cpuinfo model name : Intel(R) Xeon(R) Gold 5122 CPU @ 3.60GHz 4 "physical id"s (chips) 32 "processors" cores, siblings (Caution: counting these is hw and system dependent. The following excerpts from /proc/cpuinfo might not be reliable. Use with caution.) cpu cores : 4 siblings : 8 physical 0: cores 1 5 9 13 physical 1: cores 0 5 9 13 physical 2: cores 1 5 9 13 physical 3: cores 1 2 5 11 cache size : 16896 KB From /proc/meminfo MemTotal: 395927580 kB HugePages_Total: 0 Hugepagesize: 2048 kB From /etc/*release* /etc/*version* SuSE-release: SUSE Linux Enterprise Server 12 (x86_64) VERSION = 12 PATCHLEVEL = 2 # This file is deprecated and will be removed in a future service pack or release. # Please check /etc/os-release for details about this release. os-release: NAME="SLES" VERSION="12-SP2" VERSION_ID="12.2" PRETTY_NAME="SUSE Linux Enterprise Server 12 SP2" ID="sles" ANSI_COLOR="0;32" CPE_NAME="cpe:/o:suse:sles:12:sp2" uname -a: Linux linux-mcua 4.4.21-68-default #1 SMP Tue Oct 18 18:19:37 UTC 2016 (63cf368) x86_64 x86_64 x86_64 GNU/Linux run-level 3 Nov 20 11:24 SPEC is set to: /home/cpu2006 Filesystem Type Size Used Avail Use% Mounted on /dev/sdb4 xfs 852G 73G 780G 9% /home Additional information from dmidecode: Warning: Use caution when you interpret this section. The 'dmidecode' program reads system data which is "intended to allow hardware to be accurately determined", but the intent may not be met, as there are frequent changes to hardware, firmware, and the "DMTF SMBIOS" standard. BIOS HPE U34 09/29/2017 Memory: 48x UNKNOWN NOT AVAILABLE 8 GB 2 rank 2666 MHz (End of data from sysinfo program) General Notes ------------- Environment variables set by runspec before the start of the run: LD_LIBRARY_PATH = "/home/cpu2006/libs/32:/home/cpu2006/libs/64:/home/cpu2006/sh10.2" Binaries compiled on a system with 1x Intel Core i7-4790 CPU + 32GB RAM memory using Redhat Enterprise Linux 7.2 Base Compiler Invocation ------------------------ C benchmarks: icc -m32 -L/opt/intel/compilers_and_libraries_2018.0.082/linux/lib/ia32 C++ benchmarks: icpc -m32 -L/opt/intel/compilers_and_libraries_2018.0.082/linux/lib/ia32 Base Portability Flags ---------------------- 400.perlbench: -D_FILE_OFFSET_BITS=64 -DSPEC_CPU_LINUX_IA32 401.bzip2: -D_FILE_OFFSET_BITS=64 403.gcc: -D_FILE_OFFSET_BITS=64 429.mcf: -D_FILE_OFFSET_BITS=64 445.gobmk: -D_FILE_OFFSET_BITS=64 456.hmmer: -D_FILE_OFFSET_BITS=64 458.sjeng: -D_FILE_OFFSET_BITS=64 462.libquantum: -D_FILE_OFFSET_BITS=64 -DSPEC_CPU_LINUX 464.h264ref: -D_FILE_OFFSET_BITS=64 471.omnetpp: -D_FILE_OFFSET_BITS=64 473.astar: -D_FILE_OFFSET_BITS=64 483.xalancbmk: -D_FILE_OFFSET_BITS=64 -DSPEC_CPU_LINUX Base Optimization Flags ----------------------- C benchmarks: -xCORE-AVX512 -ipo -O3 -no-prec-div -qopt-prefetch -qopt-mem-layout-trans=3 C++ benchmarks: -xCORE-AVX512 -ipo -O3 -no-prec-div -qopt-prefetch -qopt-mem-layout-trans=3 -Wl,-z,muldefs -L/home/cpu2006/sh10.2 -lsmartheap Base Other Flags ---------------- C benchmarks: 403.gcc: -Dalloca=_alloca The flags files that were used to format this result can be browsed at http://www.spec.org/cpu2006/flags/Intel-ic17.0-official-linux64-revF.html http://www.spec.org/cpu2006/flags/HPE-Platform-Flags-Intel-V1.2-SKX-revG.html You can also download the XML flags sources by saving the following links: http://www.spec.org/cpu2006/flags/Intel-ic17.0-official-linux64-revF.xml http://www.spec.org/cpu2006/flags/HPE-Platform-Flags-Intel-V1.2-SKX-revG.xml SPEC and SPECint are registered trademarks of the Standard Performance Evaluation Corporation. All other brand and product names appearing in this result are trademarks or registered trademarks of their respective holders. ----------------------------------------------------------------------------- For questions about this result, please contact the tester. For other inquiries, please contact webmaster@spec.org. Copyright 2006-2017 Standard Performance Evaluation Corporation Tested with SPEC CPU2006 v1.2. Report generated on Tue Dec 12 17:07:05 2017 by CPU2006 ASCII formatter v6932. Originally published on 12 December 2017.