SPEC(R) CINT2006 Summary Cisco Systems Cisco UCS C460 M4 (Intel Xeon E7-4850 v3, 2.20 GHz) Mon Jul 6 05:34:58 2015 CPU2006 License: 9019 Test date: Jul-2015 Test sponsor: Cisco Systems Hardware availability: May-2015 Tested by: Cisco Systems Software availability: Nov-2014 Base Base Base Peak Peak Peak Benchmarks Copies Run Time Rate Copies Run Time Rate -------------- ------ --------- --------- ------ --------- --------- 400.perlbench 112 720 1520 S 400.perlbench 112 731 1500 S 400.perlbench 112 720 1520 * 401.bzip2 112 1129 957 S 401.bzip2 112 1130 957 * 401.bzip2 112 1130 956 S 403.gcc 112 604 1490 S 403.gcc 112 604 1490 * 403.gcc 112 602 1500 S 429.mcf 112 413 2470 * 429.mcf 112 414 2470 S 429.mcf 112 413 2470 S 445.gobmk 112 822 1430 S 445.gobmk 112 823 1430 S 445.gobmk 112 822 1430 * 456.hmmer 112 355 2950 S 456.hmmer 112 367 2850 S 456.hmmer 112 359 2910 * 458.sjeng 112 901 1500 * 458.sjeng 112 902 1500 S 458.sjeng 112 901 1500 S 462.libquantum 112 119 19600 S 462.libquantum 112 119 19600 * 462.libquantum 112 118 19600 S 464.h264ref 112 1018 2430 S 464.h264ref 112 1016 2440 S 464.h264ref 112 1017 2440 * 471.omnetpp 112 764 916 * 471.omnetpp 112 768 911 S 471.omnetpp 112 763 917 S 473.astar 112 722 1090 S 473.astar 112 726 1080 S 473.astar 112 726 1080 * 483.xalancbmk 112 368 2100 S 483.xalancbmk 112 366 2110 S 483.xalancbmk 112 367 2110 * ============================================================================== 400.perlbench 112 720 1520 * 401.bzip2 112 1130 957 * 403.gcc 112 604 1490 * 429.mcf 112 413 2470 * 445.gobmk 112 822 1430 * 456.hmmer 112 359 2910 * 458.sjeng 112 901 1500 * 462.libquantum 112 119 19600 * 464.h264ref 112 1017 2440 * 471.omnetpp 112 764 916 * 473.astar 112 726 1080 * 483.xalancbmk 112 367 2110 * SPECint(R)_rate_base2006 1970 SPECint_rate2006 Not Run HARDWARE -------- CPU Name: Intel Xeon E7-4850 v3 CPU Characteristics: Intel Turbo Boost Technology up to 2.80 GHz CPU MHz: 2200 FPU: Integrated CPU(s) enabled: 56 cores, 4 chips, 14 cores/chip, 2 threads/core CPU(s) orderable: 2,4 chip Primary Cache: 32 KB I + 32 KB D on chip per core Secondary Cache: 256 KB I+D on chip per core L3 Cache: 35 MB I+D on chip per chip Other Cache: None Memory: 1 TB (64 x 16 GB 2Rx4 PC4-2133P-R, running at 1333 MHz) Disk Subsystem: 1 x 600 GB SAS, 10K RPM Other Hardware: None SOFTWARE -------- Operating System: SUSE Linux Enterprise Server 12 (x86_64) 3.12.28-4-default Compiler: C/C++: Version 15.0.0.090 of Intel C++ Studio XE for Linux Auto Parallel: No File System: xfs System State: Run level 3 (multi-user) Base Pointers: 32-bit Peak Pointers: 32/64-bit Other Software: Microquill SmartHeap V10.0 Submit Notes ------------ The numactl mechanism was used to bind copies to processors. The config file option 'submit' was used to generate numactl commands to bind each copy to a specific processor. For details, please see the config file. Operating System Notes ---------------------- Stack size set to unlimited using "ulimit -s unlimited" Platform Notes -------------- BIOS Configuration: CPU performance set to Enterprise Power Technology set to Performance Energy Performance BIAS setting set to Balanced Performance Memory RAS configuration set to Maximum Performance Memory Power Saving Mode set to Disabled Sysinfo program /opt/cpu2006-1.2/config/sysinfo.rev6914 $Rev: 6914 $ $Date:: 2014-06-25 #$ e3fbb8667b5a285932ceab81e28219e1 running on sles12 Mon Jul 6 02:34:59 2015 This section contains SUT (System Under Test) info as seen by some common utilities. To remove or add to this section, see: http://www.spec.org/cpu2006/Docs/config.html#sysinfo From /proc/cpuinfo model name : Intel(R) Xeon(R) CPU E7-4850 v3 @ 2.20GHz 4 "physical id"s (chips) 112 "processors" cores, siblings (Caution: counting these is hw and system dependent. The following excerpts from /proc/cpuinfo might not be reliable. Use with caution.) cpu cores : 14 siblings : 28 physical 0: cores 0 1 2 3 4 5 6 8 9 10 11 12 13 14 physical 1: cores 0 1 2 3 4 5 6 8 9 10 11 12 13 14 physical 2: cores 0 1 2 3 4 5 6 8 9 10 11 12 13 14 physical 3: cores 0 1 2 3 4 5 6 8 9 10 11 12 13 14 cache size : 35840 KB From /proc/meminfo MemTotal: 1058662276 kB HugePages_Total: 0 Hugepagesize: 2048 kB From /etc/*release* /etc/*version* SuSE-release: SUSE Linux Enterprise Server 12 (x86_64) VERSION = 12 PATCHLEVEL = 0 # This file is deprecated and will be removed in a future service pack or release. # Please check /etc/os-release for details about this release. os-release: NAME="SLES" VERSION="12" VERSION_ID="12" PRETTY_NAME="SUSE Linux Enterprise Server 12" ID="sles" ANSI_COLOR="0;32" CPE_NAME="cpe:/o:suse:sles:12" uname -a: Linux sles12 3.12.28-4-default #1 SMP Thu Sep 25 17:02:34 UTC 2014 (9879bd4) x86_64 x86_64 x86_64 GNU/Linux run-level 3 Jul 6 02:23 SPEC is set to: /opt/cpu2006-1.2 Filesystem Type Size Used Avail Use% Mounted on /dev/sda2 xfs 500G 104G 397G 21% / Additional information from dmidecode: Warning: Use caution when you interpret this section. The 'dmidecode' program reads system data which is "intended to allow hardware to be accurately determined", but the intent may not be met, as there are frequent changes to hardware, firmware, and the "DMTF SMBIOS" standard. BIOS Cisco Systems, Inc. C460M4.2.0.5b.0.052420152246 05/24/2015 Memory: 64x 0xCE00 M393A2G40DB0-CPB 16 GB 2 rank 1333 MHz 32x NO DIMM NO DIMM 1333 MHz (End of data from sysinfo program) General Notes ------------- Environment variables set by runspec before the start of the run: LD_LIBRARY_PATH = "/opt/cpu2006-1.2/libs/32:/opt/cpu2006-1.2/libs/64:/opt/cpu2006-1.2/sh" Binaries compiled on a system with 1x Core i5-4670K CPU + 16GB memory using RedHat EL 7.0 Transparent Huge Pages enabled with: echo always > /sys/kernel/mm/transparent_hugepage/enabled Filesystem page cache cleared with: echo 1> /proc/sys/vm/drop_caches runspec command invoked through numactl i.e.: numactl --interleave=all runspec Base Compiler Invocation ------------------------ C benchmarks: icc -m32 -L/opt/intel/composer_xe_2015/lib/ia32 C++ benchmarks: icpc -m32 -L/opt/intel/composer_xe_2015/lib/ia32 Base Portability Flags ---------------------- 400.perlbench: -DSPEC_CPU_LINUX_IA32 462.libquantum: -DSPEC_CPU_LINUX 483.xalancbmk: -DSPEC_CPU_LINUX Base Optimization Flags ----------------------- C benchmarks: -xCORE-AVX2 -ipo -O3 -no-prec-div -opt-prefetch -opt-mem-layout-trans=3 C++ benchmarks: -xCORE-AVX2 -ipo -O3 -no-prec-div -opt-prefetch -opt-mem-layout-trans=3 -Wl,-z,muldefs -L/sh -lsmartheap Base Other Flags ---------------- C benchmarks: 403.gcc: -Dalloca=_alloca The flags files that were used to format this result can be browsed at http://www.spec.org/cpu2006/flags/Intel-ic15.0-official-linux64.html http://www.spec.org/cpu2006/flags/Cisco-Platform-Settings-V1.2-revC.20150729.html You can also download the XML flags sources by saving the following links: http://www.spec.org/cpu2006/flags/Intel-ic15.0-official-linux64.xml http://www.spec.org/cpu2006/flags/Cisco-Platform-Settings-V1.2-revC.20150729.xml SPEC and SPECint are registered trademarks of the Standard Performance Evaluation Corporation. All other brand and product names appearing in this result are trademarks or registered trademarks of their respective holders. ----------------------------------------------------------------------------- For questions about this result, please contact the tester. For other inquiries, please contact webmaster@spec.org. Copyright 2006-2015 Standard Performance Evaluation Corporation Tested with SPEC CPU2006 v1.2. Report generated on Wed Jul 29 12:11:21 2015 by CPU2006 ASCII formatter v6932. Originally published on 28 July 2015.